129 lines
4.5 KiB
C
129 lines
4.5 KiB
C
//*****************************************************************************
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// boot_multicore_slave.c
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//
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// Provides functions to allow booting of slave core in multicore system
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//
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// Version : 151217
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//
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//*****************************************************************************
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//
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// Copyright 2014-2015, NXP
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// All rights reserved.
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//
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// Software that is described herein is for illustrative purposes only
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// which provides customers with programming information regarding the
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// LPC products. This software is supplied "AS IS" without any warranties of
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// any kind, and NXP Semiconductors and its licensor disclaim any and
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// all warranties, express or implied, including all implied warranties of
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// merchantability, fitness for a particular purpose and non-infringement of
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// intellectual property rights. NXP Semiconductors assumes no responsibility
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// or liability for the use of the software, conveys no license or rights under any
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// patent, copyright, mask work right, or any other intellectual property rights in
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// or to any products. NXP Semiconductors reserves the right to make changes
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// in the software without notification. NXP Semiconductors also makes no
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// representation or warranty that such application will be suitable for the
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// specified use without further testing or modification.
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//
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// Permission to use, copy, modify, and distribute this software and its
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// documentation is hereby granted, under NXP Semiconductors' and its
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// licensor's relevant copyrights in the software, without fee, provided that it
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// is used in conjunction with NXP Semiconductors microcontrollers. This
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// copyright, permission, and disclaimer notice must appear in all copies of
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// this code.
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//*****************************************************************************
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#if defined (__MULTICORE_MASTER_SLAVE_M0SLAVE) || \
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defined (__MULTICORE_MASTER_SLAVE_M4SLAVE)
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#if defined (__USE_LPCOPEN)
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#include "chip.h"
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#else
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#include <stdint.h>
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#define SYSCON_BASE ((uint32_t) 0x40000000)
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#if defined (__LPC5410X__)
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#define CPBOOT (((volatile uint32_t *) (SYSCON_BASE + 0x304)))
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#define CPSTACK (((volatile uint32_t *) (SYSCON_BASE + 0x308)))
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#define CPUCTRL (((volatile uint32_t *) (SYSCON_BASE + 0x300)))
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#elif defined (__LPC5411X__)
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#define CPBOOT (((volatile uint32_t *) (SYSCON_BASE + 0x804)))
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#define CPSTACK (((volatile uint32_t *) (SYSCON_BASE + 0x808)))
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#define CPUCTRL (((volatile uint32_t *) (SYSCON_BASE + 0x800)))
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#else
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#error Unrecognised MCU - cannot resolve Dual-CPU related registers
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#endif
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#define CPUCTRL_KEY ((uint32_t)(0x0000C0C4 << 16))
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#define CM4_CLK_ENA (1<<2)
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#define CM0_CLK_ENA (1<<3)
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#define CM4_RESET_ENA (1<<4)
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#define CM0_RESET_ENA (1<<5)
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#define CM4_SLEEPCON (1<<6)
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#if defined (CORE_M4)
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void Chip_CPU_CM0Boot(uint32_t *coentry, uint32_t *costackptr)
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{
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volatile uint32_t *u32REG, u32Val;
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*CPSTACK = (uint32_t) costackptr;
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*CPBOOT = (uint32_t) coentry;
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u32REG = (uint32_t *) CPUCTRL;
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u32Val = *u32REG;
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// Enable slave clock and reset
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u32Val |= (CPUCTRL_KEY | ((CM0_CLK_ENA | CM0_RESET_ENA) & 0x7F));
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*u32REG = u32Val;
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// Clear slave reset
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u32Val &= ~CM0_RESET_ENA;
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*u32REG = u32Val;
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}
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#else // !defined CORE_M4
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void Chip_CPU_CM4Boot(uint32_t *coentry, uint32_t *costackptr)
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{
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volatile uint32_t *u32REG, u32Val;
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*CPSTACK = (uint32_t) costackptr;
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*CPBOOT = (uint32_t) coentry;
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u32REG = (uint32_t *) CPUCTRL;
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u32Val = *u32REG;
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// Enable slave clock and reset
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u32Val |= (CPUCTRL_KEY | ((CM4_CLK_ENA | CM4_RESET_ENA) & 0x7F));
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*u32REG = u32Val;
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// Clear slave reset
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u32Val &= ~CM0_RESET_ENA;
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*u32REG = u32Val;
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}
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#endif // defined CORE_M4
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#endif // __USE_LPCOPEN
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#if defined (CORE_M4)
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extern uint8_t __core_m0slave_START__;
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#else
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extern uint8_t __core_m4slave_START__;
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#endif
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void boot_multicore_slave(void) {
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#if defined (CORE_M4)
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unsigned int *slavevectortable_ptr = (unsigned int *)&__core_m0slave_START__;
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#else
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unsigned int *slavevectortable_ptr = (unsigned int *)&__core_m4slave_START__;
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#endif
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volatile unsigned int resetaddr;
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volatile unsigned int spaddr;
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spaddr = *slavevectortable_ptr;
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resetaddr = *(slavevectortable_ptr+1);
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#if defined (CORE_M4)
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Chip_CPU_CM0Boot((uint32_t *)resetaddr, (uint32_t *)spaddr);
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#else
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Chip_CPU_CM4Boot((uint32_t *)resetaddr, (uint32_t *)spaddr);
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#endif
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}
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#endif // defined (__MULTICORE_MASTER_SLAVE_M0SLAVE) ||
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// (__MULTICORE_MASTER_SLAVE_M4SLAVE)
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