initial check in based on SVN revision 575
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257
board/clock_config.c
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257
board/clock_config.c
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/***********************************************************************************************************************
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* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
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* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
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**********************************************************************************************************************/
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/*
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* How to set up clock using clock driver functions:
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*
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* 1. Setup clock sources.
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*
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* 2. Setup voltage for the fastest of the clock outputs
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*
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* 3. Set up wait states of the flash.
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*
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* 4. Set up all dividers.
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*
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* 5. Set up all selectors to provide selected clocks.
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*/
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/* clang-format off */
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/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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!!GlobalInfo
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product: Clocks v11.0
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processor: LPC54114J256
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package_id: LPC54114J256BD64
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mcu_data: ksdk2_0
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processor_version: 13.0.1
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board: LPCXpresso54114
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
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/* clang-format on */
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#include "fsl_power.h"
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#include "fsl_clock.h"
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#include "clock_config.h"
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/*******************************************************************************
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************************ BOARD_InitBootClocks function ************************
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******************************************************************************/
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void BOARD_InitBootClocks(void)
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{
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BOARD_BootClockPLL150M();
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}
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/*******************************************************************************
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******************** Configuration BOARD_BootClockFRO12M **********************
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******************************************************************************/
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/* clang-format off */
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/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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!!Configuration
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name: BOARD_BootClockFRO12M
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outputs:
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- {id: System_clock.outFreq, value: 12 MHz}
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
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/* clang-format on */
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/*******************************************************************************
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* Variables for BOARD_BootClockFRO12M configuration
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******************************************************************************/
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/*******************************************************************************
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* Code for BOARD_BootClockFRO12M configuration
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******************************************************************************/
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void BOARD_BootClockFRO12M(void)
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{
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#ifndef SDK_SECONDARY_CORE
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/*!< Set up the clock sources */
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/*!< Set up FRO */
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POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */
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CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
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CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without accidentally
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being below the voltage for current speed */
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POWER_SetVoltageForFreq(12000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
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CLOCK_SetFLASHAccessCyclesForFreq(12000000U); /*!< Set FLASH wait states for core */
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/*!< Set up dividers */
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CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
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/*!< Set up clock selectors - Attach clocks to the peripheries */
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CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO12M */
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/*!< Set SystemCoreClock variable. */
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SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;
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#endif
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}
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/*******************************************************************************
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******************* Configuration BOARD_BootClockFROHF48M *********************
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******************************************************************************/
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/* clang-format off */
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/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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!!Configuration
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name: BOARD_BootClockFROHF48M
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outputs:
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- {id: System_clock.outFreq, value: 48 MHz}
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settings:
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- {id: SYSCON.MAINCLKSELA.sel, value: SYSCON.fro_hf}
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
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/* clang-format on */
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/*******************************************************************************
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* Variables for BOARD_BootClockFROHF48M configuration
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******************************************************************************/
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/*******************************************************************************
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* Code for BOARD_BootClockFROHF48M configuration
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******************************************************************************/
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void BOARD_BootClockFROHF48M(void)
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{
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#ifndef SDK_SECONDARY_CORE
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/*!< Set up the clock sources */
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/*!< Set up FRO */
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POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */
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CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
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CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without accidentally
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being below the voltage for current speed */
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POWER_SetVoltageForFreq(48000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
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CLOCK_SetFLASHAccessCyclesForFreq(48000000U); /*!< Set FLASH wait states for core */
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CLOCK_SetupFROClocking(48000000U); /*!< Set up high frequency FRO output to selected frequency */
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/*!< Set up dividers */
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CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
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/*!< Set up clock selectors - Attach clocks to the peripheries */
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CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */
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/*!< Set SystemCoreClock variable. */
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SystemCoreClock = BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK;
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#endif
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}
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/*******************************************************************************
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******************* Configuration BOARD_BootClockFROHF96M *********************
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******************************************************************************/
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/* clang-format off */
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/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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!!Configuration
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name: BOARD_BootClockFROHF96M
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outputs:
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- {id: System_clock.outFreq, value: 96 MHz}
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settings:
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- {id: SYSCON.MAINCLKSELA.sel, value: SYSCON.fro_hf}
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sources:
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- {id: SYSCON.fro_hf.outFreq, value: 96 MHz}
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
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/* clang-format on */
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/*******************************************************************************
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* Variables for BOARD_BootClockFROHF96M configuration
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******************************************************************************/
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/*******************************************************************************
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* Code for BOARD_BootClockFROHF96M configuration
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******************************************************************************/
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void BOARD_BootClockFROHF96M(void)
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{
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#ifndef SDK_SECONDARY_CORE
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/*!< Set up the clock sources */
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/*!< Set up FRO */
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POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */
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CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
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CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without accidentally
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being below the voltage for current speed */
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POWER_SetVoltageForFreq(96000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
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CLOCK_SetFLASHAccessCyclesForFreq(96000000U); /*!< Set FLASH wait states for core */
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CLOCK_SetupFROClocking(96000000U); /*!< Set up high frequency FRO output to selected frequency */
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/*!< Set up dividers */
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CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
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/*!< Set up clock selectors - Attach clocks to the peripheries */
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CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */
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/*!< Set SystemCoreClock variable. */
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SystemCoreClock = BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK;
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#endif
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}
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/*******************************************************************************
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******************** Configuration BOARD_BootClockPLL150M *********************
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******************************************************************************/
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/* clang-format off */
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/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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!!Configuration
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name: BOARD_BootClockPLL150M
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called_from_default_init: true
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outputs:
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- {id: PLL_clock.outFreq, value: 144 MHz}
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- {id: System_clock.outFreq, value: 144 MHz}
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settings:
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- {id: PLL_Mode, value: Normal}
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- {id: SYSCON.DIRECTO.sel, value: SYSCON.PLL}
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- {id: SYSCON.MAINCLKSELA.sel, value: SYSCON.clk_in}
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- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL_BYPASS}
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- {id: SYSCON.M_MULT.scale, value: '48', locked: true}
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- {id: SYSCON.N_DIV.scale, value: '8', locked: true}
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- {id: SYSCON.PLL_BYPASS.sel, value: SYSCON.DIRECTO}
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- {id: SYSCON.SYSPLLCLKSEL.sel, value: SYSCON.clk_in}
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sources:
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- {id: SYSCON.clk_in.outFreq, value: 24 MHz, enabled: true}
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
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/* clang-format on */
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/*******************************************************************************
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* Variables for BOARD_BootClockPLL150M configuration
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******************************************************************************/
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/*******************************************************************************
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* Code for BOARD_BootClockPLL150M configuration
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******************************************************************************/
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void BOARD_BootClockPLL150M(void)
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{
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#ifndef SDK_SECONDARY_CORE
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/*!< Set up the clock sources */
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/*!< Set up FRO */
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POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */
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CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
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CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without accidentally
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being below the voltage for current speed */
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POWER_SetVoltageForFreq(144000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
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CLOCK_SetFLASHAccessCyclesForFreq(144000000U); /*!< Set FLASH wait states for core */
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/*!< Set up PLL */
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CLOCK_AttachClk(kEXT_CLK_to_SYS_PLL); /*!< Switch PLL clock source selector to EXT_CLK */
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const pll_setup_t pllSetup = {
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.syspllctrl = SYSCON_SYSPLLCTRL_BANDSEL_MASK | SYSCON_SYSPLLCTRL_SELI(52U) | SYSCON_SYSPLLCTRL_SELP(25U) | SYSCON_SYSPLLCTRL_DIRECTO_MASK,
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.syspllndec = SYSCON_SYSPLLNDEC_NDEC(44U),
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.syspllpdec = SYSCON_SYSPLLPDEC_PDEC(2U),
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.syspllssctrl = {(SYSCON_SYSPLLSSCTRL0_MDEC(32682U) | SYSCON_SYSPLLSSCTRL0_SEL_EXT_MASK),0x0U},
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.pllRate = 144000000U,
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.flags = PLL_SETUPFLAG_POWERUP
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};
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CLOCK_SetPLLFreq(&pllSetup); /*!< Configure PLL to the desired values */
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/* PLL input more than 20 MHz */
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/* SYSTICK is used for waiting for PLL stabilization */
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CLOCK_SetClkDiv(kCLOCK_DivSystickClk, 0U, true); /*!< Reset SysTick divider counter and halt it */
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CLOCK_SetClkDiv(kCLOCK_DivSystickClk, 3U, false); /*!< Set SysTick divider to value 3 */
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SysTick->LOAD = 27999UL; /*!< Set SysTick count value */
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SysTick->VAL = 0UL; /*!< Reset current count value */
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SysTick->CTRL = SysTick_CTRL_ENABLE_Msk; /*!< Enable SYSTICK */
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while((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != SysTick_CTRL_COUNTFLAG_Msk){} /*!< Waiting for PLL stabilization */
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SysTick->CTRL = 0UL; /*!< Stop SYSTICK */
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/*!< Set up dividers */
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CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
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/*!< Set up clock selectors - Attach clocks to the peripheries */
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CLOCK_AttachClk(kSYS_PLL_to_MAIN_CLK); /*!< Switch MAIN_CLK to SYS_PLL */
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SYSCON->MAINCLKSELA = ((SYSCON->MAINCLKSELA & ~SYSCON_MAINCLKSELA_SEL_MASK) | SYSCON_MAINCLKSELA_SEL(1U)); /*!< Switch MAINCLKSELA to EXT_CLK even it is not used for MAINCLKSELB */
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/*!< Set SystemCoreClock variable. */
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SystemCoreClock = BOARD_BOOTCLOCKPLL150M_CORE_CLOCK;
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#endif
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}
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