#ifndef _DDS_H
#define _DDS_H

#include "spi.h"
#include "io.h"

#define	TX_SYS_CLK		12000000	// 12MHZ
#define	DDS_CLK			TX_SYS_CLK



#define FREQ_MAX_NUM	 50		//Max number of frequencies allowed
#define	FREQ_MIN	0
#define	FREQ0_REG	0x4000		// Address of internal 9838 register
#define FRQ_CTRL_WORD1	0x2100	// Control register with Reset bit active
#define	FRQ_CTRL_WORD2	0x2000	// Exit Reset Control Word
#define PHASE_RESET		0xC000	// PHASE Register 0 = 0;

#define RAMP_CTRL_WORD1	    0x2102
#define RAMP_CTRL_WORD2	    0x2002
#define RAMP_CTRL_WORD3	    0x2002	// TODO Places wavegen in sleep mode
#define SLP_CTRL_WRD        0x2180		// Power down unused DDS
#define SLP_CTRL_WRD2       0x21C0

#define BCAST_MIN	3140
#define BCAST_MAX 	200000
#define	DUMMY_FRQ	250
#define MIN_BLOCK_FREQ	20000
#define MASK_15		0b00000000
#define MASK_58		0b00001000
#define MASK_144	0b00011000
#define CLK_MASK_BITS 0b11100111
#define	MAX_LD_FREQ 10000

//FREQUENCY PACKING - from RX so it has extra fields
#define FREQ_PACK_MASK_FREQ		0x0007ffff	//target frequency				bits 0 - 18
#define FREQ_PACK_MASK_TYPE		0x00380000	//3-bit field for FREQ_TYPE_t. 	bits 19 - 21
#define FREQ_PACK_SHIFT_TYPE	19			//Frequency type shift
#define FREQ_PACK_MASK_ENABLED	0x80000000	//enabled mask
#define FREQ_PACK_SHIFT_ENABLED	31			//enabled shift					bit 31
#define FREQ_PACK_MASK_INMENU	0x40000000	//inMenu mask
#define FREQ_PACK_SHIFT_INMENU	30			//inMenu shift					bit 30

//Locate direction (LD)
#define FREQ_LD_MAX_FREQUENCY	10000		//LD runs at or below this frequency
#define FREQ_LD_SWITCH_POINT	1500		//At or below this freq, f2 is f1 * 2. above this f2 = f1 / 2

typedef struct
{
    SPI_MODE_t mode;
    
    uint32_t frequency;

    // reset pin
    gpio_pin_t resetPin;

} dds_t;

void dds_init(dds_t *dds, SPI_MODE_t mode, gpio_pin_t resetPin);
void dds_reset(dds_t *dds, bool reset);
void dds_sleep(dds_t *dds, bool sleep, bool disableDAC);
#endif