63 lines
1.9 KiB
C
63 lines
1.9 KiB
C
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#ifndef _DDS_H
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#define _DDS_H
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#include "spi.h"
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#include "io.h"
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#define TX_SYS_CLK 12000000 // 12MHZ
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#define DDS_CLK TX_SYS_CLK
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#define RAMP_300KHZ 6710886
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#define FREQ_MAX_NUM 50 //Max number of frequencies allowed
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#define FREQ_MIN 0
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#define FREQ0_REG 0x4000 // Address of internal 9838 register
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#define FRQ_CTRL_WORD1 0x2100 // Control register with Reset bit active
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#define FRQ_CTRL_WORD2 0x2000 // Exit Reset Control Word
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#define PHASE_RESET 0xC000 // PHASE Register 0 = 0;
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#define RAMP_CTRL_WORD1 0x2102
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#define RAMP_CTRL_WORD2 0x2002
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#define RAMP_CTRL_WORD3 0x2002 // TODO Places wavegen in sleep mode
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#define SLP_CTRL_WRD 0x2180 // Power down unused DDS
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#define SLP_CTRL_WRD2 0x21C0
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#define BCAST_MIN 3140
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#define BCAST_MAX 200000
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#define DUMMY_FRQ 250
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#define MIN_BLOCK_FREQ 20000
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#define MASK_15 0b00000000
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#define MASK_58 0b00001000
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#define MASK_144 0b00011000
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#define CLK_MASK_BITS 0b11100111
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#define MAX_LD_FREQ 10000
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//FREQUENCY PACKING - from RX so it has extra fields
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#define FREQ_PACK_MASK_FREQ 0x0007ffff //target frequency bits 0 - 18
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#define FREQ_PACK_MASK_TYPE 0x00380000 //3-bit field for FREQ_TYPE_t. bits 19 - 21
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#define FREQ_PACK_SHIFT_TYPE 19 //Frequency type shift
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#define FREQ_PACK_MASK_ENABLED 0x80000000 //enabled mask
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#define FREQ_PACK_SHIFT_ENABLED 31 //enabled shift bit 31
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#define FREQ_PACK_MASK_INMENU 0x40000000 //inMenu mask
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#define FREQ_PACK_SHIFT_INMENU 30 //inMenu shift bit 30
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//Locate direction (LD)
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#define FREQ_LD_MAX_FREQUENCY 10000 //LD runs at or below this frequency
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#define FREQ_LD_SWITCH_POINT 1500 //At or below this freq, f2 is f1 * 2. above this f2 = f1 / 2
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typedef struct
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{
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SPI_MODE_t mode;
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uint32_t frequency;
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// reset pin
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gpio_pin_t resetPin;
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} dds_t;
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void dds_init(dds_t *dds, SPI_MODE_t mode, gpio_pin_t resetPin);
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void dds_reset(dds_t *dds, bool reset);
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void dds_sleep(dds_t *dds, bool sleep, bool disableDAC);
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#endif
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